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[Other resource] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23722 | Author: Jawen | Hits:

[Other resource] byvhdstopwatchl

Description: 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design)
Platform: | Size: 1995 | Author: 方周 | Hits:

[Embeded-SCM Develop] VHDLRAM

Description: 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware description language features and design ideas, vhdl use hardware description language computer science experiments RAM memory design, Description of key computer components of the traditional principle experiment to transplant platform based on the idea of CPLD
Platform: | Size: 30907 | Author: 刘浏 | Hits:

[Embeded-SCM Develop] dualportRAM

Description: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Platform: | Size: 90116 | Author: 王雪松 | Hits:

[Other resource] S3Demo

Description: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Platform: | Size: 731568 | Author: Roy Hsu | Hits:

[Other resource] cf_vhdl

Description: CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
Platform: | Size: 700616 | Author: gbh | Hits:

[Other resource] MyCPU16

Description: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计
Platform: | Size: 1089412 | Author: 孙冰 | Hits:

[VHDL-FPGA-Verilog] RTL_Memory_AN

Description:
Platform: | Size: 207872 | Author: lijainqiu | Hits:

[VHDL-FPGA-Verilog] ram_r_w

Description: 用vhdl语言描写的存储器的读写，通俗易懂，简单实用。-Using VHDL language description of the memory read and write, user-friendly, simple and practical.
Platform: | Size: 39936 | Author: wuyub | Hits:

[VHDL-FPGA-Verilog] SYNTHPIC.ZIP

Description: The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting -The Synthetic PICVerion 1.1This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.It is not, and is not intended as, a high fidelity circuit simulation.This package includes the following files. Note that the license agreementis stated in the main VHDL file , PICCPU.VHD and common questions are answeredin the file SYNTHPIC.TXTFiles: README.TXT This file .. SYNTHPIC.TXT Questions and AnswersPICCPU.VHD Main processor VHDL filePICALU.VHD ALU for the PICCPUPICREGS.VHD Data memoryPICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it.TEST2.ASM Another test program. . TEST3.ASM Yet another .. TEST4.ASM Yet another .. TEST5.ASM Yet another .. TEST6.ASM Yet another .. HEX2VHDL.CPP Utility for converting
Platform: | Size: 48128 | Author: likui | Hits:

[VHDL-FPGA-Verilog] vga_card

Description: VGA模块的VHDL代码和软件驱动，可作为外设挂接在Avalon总线上。用一块SRAM作为显存，双缓存切换模式。-VGA module VHDL code and software drivers can be articulated as a peripheral bus in Avalon. As with a piece of SRAM memory, dual-mode cache switching.
Platform: | Size: 6144 | Author: ctqy | Hits:

[VHDL-FPGA-Verilog] Ring_mem_VHDL

Description: 响铃和内存管理功能的VHDL语言，用于程控交换机中的Xillinx芯片与DSP和ADDA等芯片配合实现交换机的功能-Ringing and memory management features VHDL language, for program-controlled switchboards in Xillinx and ADDA chip and DSP chip, etc. with the function of switches realize
Platform: | Size: 12288 | Author: alanwater | Hits:

[VHDL-FPGA-Verilog] singt

Description: 用VHDL语言描述的用锁存器，加法计数器，ROM存储器构成的RTL图-VHDL language used to describe the use of latches, adding counters, ROM memory map consisting of RTL
Platform: | Size: 340992 | Author: 王洁 | Hits:

[VHDL-FPGA-Verilog] fifo_memory

Description: 用vhdl设计的一个FIFO存储器-Vhdl design with a FIFO memory
Platform: | Size: 1024 | Author: jiangp | Hits:

[VHDL-FPGA-Verilog] del_ctrl_rtl

Description: A VHDL logical example of memory delay controller -A VHDL logical example of memory delay controller
Platform: | Size: 1024 | Author: gios78 | Hits:

[VHDL-FPGA-Verilog] instmemory

Description: Instruction memory in VHDL
Platform: | Size: 1024 | Author: Abdelaziz | Hits:

[Embeded-SCM Develop] DIANZIQIN

Description: 实现琴键记忆及动态显示的电子琴VHDL源程序，经FPGA验证可行-Achieve the keys of the keyboard memory and dynamic display VHDL source code, after FPGA validation feasible
Platform: | Size: 2048 | Author: 王宇坤 | Hits:

[VHDL-FPGA-Verilog] Fpgamemtest

Description: 这个是用vhdl语言描写的关于测试FPGA内存的代码。用reset复位，包括.vhdl .ucf .bit文件。我只上传了这3个最重要的。-test memory,including .vhdl .ucf and .bit file~
Platform: | Size: 9216 | Author: 唐艺洋 | Hits:

[VHDL-FPGA-Verilog] proc

Description: vhdl processor,5 commands,memory,testbench
Platform: | Size: 1229824 | Author: ulyana | Hits:

[VHDL-FPGA-Verilog] write_reg

Description: 用VHDL语言编写的写存储器程序，可下载在FPGA中使用-VHDL language used to write memory program can be downloaded in the FPGA using
Platform: | Size: 6144 | Author: cloudy | Hits:
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